Semiconductor devices have been developed to afford a higher degree of reliability and integration. It is desirable that these highly integrated circuit devices have multi-level interconnection structure on the surface of the semiconductor substrate to provide lead-out wirings to each of the semiconductor regions in the substrate.
The lead-out wirings for conventional semiconductor devices are formed by selective photo-etching of a thin metal film formed by sputtering or vacuum evaporation of metal over the semiconductor substrate. However, on the surface of the substrate, a certain degree of unevenness is unavoidable in lead-out wiring formed in that manner. Furthermore, since an overlying wiring layer is juxtaposed with an uneven underlying wiring layer, the problem of unevenness is worsened as layers are laminated and multi-level interconnections are formed.
Additionally, it is known in the art that when the metal film forming the wiring is deposited on the substrate surface, the thickness of the metal film is often insufficient at the end portions of the wiring. Moreover, the end portions of the wiring are particularly vulnerable to selective etching. As a result, the wirings may become defective and hence the reliability. Thus, with the conventional technique of selective etching, it is almost impossible to provide a highly reliable integrated circuit device, especially one having multi-level interconnection structure.